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ISL8112
Electrical Specifications
Circuit of Figure 17, and Figure 18, no load on LDO, VSEN1, VSEN2, VREF2, and VREF1, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, T A = -40°C to +100°C, unless otherwise noted.
Typical values are at T A = +25°C. (Continued)
MIN
MAX
PARAMETER
LDOREF Input Voltage
CONDITIONS
Fixed LDO = 5V
VSEN2 Dynamic Range, V LDO = 2 x V LDOREF
(Note 3)
0.35
TYP
(Note 3)
0.30
2.25
UNITS
V
V
Fixed LDO = 3.3V
VCC-1.0
V
MODE Input Voltage
Low level (SKIP)
0.8
V
Float level (ULTRASONIC SKIP)
High level (PWM)
1.7
2.4
2.3
V
V
FS Input Voltage
Low level
0.8
V
Float level
High level
1.7
2.4
2.3
V
V
EN1, EN2 Input Voltage
Clear fault level/SMPS off level
0.8
V
Delay start level
SMPS on level
1.7
2.4
2.3
V
V
EN_LDO Input Voltage
Input Leakage Current
Rising edge
Falling edge
VFS = 0 or 5V
VEN _ = VEN_LDO = 0V or 5V
VMODE = 0V or 5V
VFB1 = 0V or 5V
VREFIN = 0V or 2.5V
VLDOREF = 0V or 2.75V
1.2
0.94
-1
-0.1
-1
-0.2
-0.2
-0.2
1.6
1.00
2.0
1.06
+1
+0.1
+1
+0.2
+0.2
+0.2
V
V
μA
μA
μA
μA
μA
μA
INTERNAL BOOT DIODE
V D Forward Voltage
I BOOT_LEAKAGE Leakage Current
PVCC - V BOOT , I F = 10mA
V BOOT = 30V, PH = 25V, PVCC = 5V
0.65
0.8
500
V
nA
MOSFET DRIVERS
UG_ Gate-Driver Sink/Source Current
LG_ Gate-Driver Source Current
LG_ Gate-Driver Sink Current
UG1, UG2 forced to 2V
LG1 (source), LG2 (source), forced to 2V
LG1 (sink), LG2 (sink), forced to 2V
2
1.7
3.3
A
A
A
UG_ Gate-Driver On-Resistance
LG_ Gate-Driver On-Resistance
BST_ - PH_ forced to 5V (Note 4)
LG_, high state (pull-up) (Note 4)
LG_, low state (pull-down) (Note 4)
1.5
2.2
0.6
4.0
5.0
1.5
Ω
Ω
Ω
Dead Time
VSEN1, VSEN2 Discharge On Resistance
LG_ Rising
UG_ Rising
15
20
20
30
25
35
50
40
ns
ns
Ω
NOTES:
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
4. Limits established by characterization and are not production tested.
6
FN6396.1
August 10, 2010
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